The present invention relates to a memory allocation mechanism, and more particularly, to a shared memory architecture, including one or more shared memory devices, applied to functional stages configured in a receiver system for processing signals from different transmitter systems (e.g., GNSS systems) and method thereof.
Please refer to FIG. 1. FIG. 1 is a block diagram illustrating a first conventional global navigation satellite system (GNSS) receiver 10. The GNSS receiver 10 supports a single GNSS system, and comprises an antenna 12 for receiving RF signals from satellites, an RF front end 14 for converting incoming RF signals into analog IF signals, an analog-to-digital converter (ADC) 16 for converting the incoming analog IF signals into digital IF signals, a plurality of functional stages 18a, 18b, 18c, and a plurality of memory devices 20a, 20b, 20c allocated to the respective functional stages 18a, 18b, 18c. The functional stage 18a is configured to perform correlation processing to provide correlation information; the functional stage 18b is configured to perform acquisition/tracking processing for ascertaining identities of the satellites and obtaining positioning information carried by signals transmitted from the identified satellites; and the functional stage 18c is configured to perform positioning/navigation processing for determining the position of the GNSS receiver 10 according to positioning information from the preceding functional stage 18b. Since details of the conventional GNSS receiver 10 have been disclosed in U.S. Pat. No. 6,526,322, and operations of the GNSS system are well known to those skilled in this art, further description is omitted here for the sake of brevity. As shown in FIG. 1, a dedicated memory device is assigned to each functional stage. In other words, the memory device 20a is configured to buffer processing data of the functional stage 18a only; the memory device 20b is configured to buffer processing data of the functional stage 18b only; and the memory device 20c is configured to buffer processing data of the functional stage 18c only.
Please refer to FIG. 2. FIG. 2 is a block diagram illustrating a second conventional GNSS receiver 30. The GNSS receiver 30 supports multiple GNSS systems (e.g., GPS, Galileo, and GLONASS), and comprises an antenna 32, an RF front end 34, an ADC 36, a plurality of functional stages 38a, 39a, 40a performing correlation processing, a plurality of functional stages 38b, 39b, 40b performing acquisition/tracking processing, a plurality of functional stages 38c, 39c, 40c performing positioning/navigation processing, and a plurality of memory devices 42a, 42b, 42c, 43a, 43b, 43c, 44a, 44b, 44c allocated to the respective functional stages 38a-38c, 39a-39c, 40a-40c. The architecture of the GNSS receiver 30 supporting multiple GNSS systems is based upon the architecture shown in FIG. 1. The components of the same name in FIG. 1 and FIG. 2 have identical operation and functionality, and further description is omitted for brevity. In the GNSS receiver 30, a signal processing chain including the functional stages 38a, 38b, 38c is implemented for processing signals from the first GNSS system (e.g., GPS), a signal processing chain including the functional stages 39a, 39b, 39c is implemented for processing signals from the second GNSS system (e.g., Galileo), and a signal processing chain including the functional stages 40a, 40b, 40c is implemented for processing signals from the third GNSS system (e.g., GLONASS). Similarly, regarding the GNSS receiver 30 supporting multiple GNSS systems, a dedicated memory device is still assigned to each functional stage. Therefore, the size and cost of the GNSS receiver 10 is unable to be reduced efficiently due to the inefficient memory allocation scheme.
Please refer to FIG. 3. FIG. 3 is a block diagram illustrating a third conventional GNSS receiver 50. The GNSS receiver 50 supports a single GNSS system, and comprises an antenna 52, an RF front end 54, an ADC 56, a plurality of functional stages 58a, 58b, 58c performing correlation processing, acquisition/tracking processing and positioning/navigation processing respectively, and a single memory device 60 commonly shared by the functional stages 58a, 58b, 58c. The internal allocation of the shared memory space in the memory device 60 for the functional stages 58a, 58b, 58c is pre-defined and fixed. Further description has been detailed in U.S. Pat. No. 6,526,322, and is omitted here for brevity. Compared to the architecture shown in FIG. 1, the GNSS receiver 50 has an improved memory allocation scheme. If the architecture shown in FIG. 3 is followed to design a GNSS receiver supporting multiple GNSS systems, a plurality of memory devices are required for respective GNSS systems.
Please refer to FIG. 4. FIG. 4 is a block diagram illustrating a fourth conventional GNSS receiver 70. The GNSS receiver 70 supports multiple GNSS systems (e.g., GPS, Galileo, and GLONASS), and comprises an antenna 72, an RF front end 74, an ADC 76, a plurality of functional stages 78a, 79a, 80a performing correlation processing, a plurality of functional stages 78b, 79b, 80b performing acquisition/tracking processing, a plurality of functional stages 78c, 79c, 80c performing positioning/navigation processing, and a plurality of memory devices 82a, 82b, 82c allocated to the respective functional stages 78a-78c, 79a-79c, 80a-80c. The components of the same name in FIG. 3 and FIG. 4 have identical operation and functionality, and further description is omitted here for brevity. Because a memory device shown in FIG. 3 is only shared by functional stages for the same GNSS system, the designer of the GNSS receiver 70 has to allocate a memory device dedicated to each GNSS system.